Veri
Sim
v1.26
Verilog in your browser · Icarus → WASM
Examples…
Gate-Level — Half Adder
Dataflow — Half Adder
Behavioral — Half Adder
Shift Register — 4-bit (sequential)
Counter — 2-bit (sequential)
Verilog-2005
Verilog/SV-2009
SystemVerilog-2012
►
Run
testbench.v
clear
open
save
design.v
clear
open
save
Console
Waveform
Synthesize
↓ dump.vcd
engine idle
Fit
scroll = zoom · drag = pan · click = cursor
Run a simulation to see waveforms.
Gates
RTL
Synthesize
scroll = zoom · drag = pan · dbl-click = fit
Press
Synthesize
to see the synthesized circuit of design.v (gate-level or RTL).