soft
fpga
v1.38
idle
📁 Examples ▾
📂
Open
💾
Save
⚡ Synthesize
▶ Run
⏭ Step
↺ Reset
1 Hz
2 Hz
5 Hz
10 Hz
20 Hz
60 Hz
250 Hz
Verilog
Netlist JSON
◫ Schematic
❓ Help
Verilog source
Console
clear
// softfpga — write Verilog, press ⚡ Synthesize, then ▶ Run
FPGA Board
LEDs (led7 → led0)
Hex display
led 7-4
led 3-0
Switches (sw7 → sw0)
iCE40UP5K · softfpga board
Information
Device
Chip
iCE40UP5K
Logic cells
5280 LUTs
Flip-flops
5280 FFs
Resource Usage
LUTs used
0
FFs used
0
Clock cycle
0
Schematic
⬇ SVG
✕ Close